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  • TriCore v6.2r2 Inspector v1.0r9 - A family of tools that provide an automated method for identifying toolset issues in compiled output code
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Arm Cortex Texas Instruments TMS570: ECC functionality 15-Sep-2026
Flash on TMS570 devices features an ECC functionality. The ECC area can be programmed automatically with values corresponding to downloaded data or you can provide your own ECC download data. The option for automatic ECC generation is located in Hardware | TI TMS570 | Configure | FLAGS Con...
Renesas RH850/U2A: Peripheral suspension 15-Sep-2026
When the OSTM timer and the suspend peripheral feature are enabled, stepping through the code might change the value in the OSTMx.CNT register. If only one core is observed, the OSTMx.CNT value will change. Conversely, if multiple cores are observed, the OSTMx.CNT value remains unchanged. ...
NXP/ST Power Architecture: Rejecting FLASH operation. No valid entry address in RCHW 15-Sep-2026
Before performing a FLASH download, winIDEA verifies if the Entry point address specified in the Symbol file (ELF file) matches the Application start address specified in the first valid RCHW record of the download image. If this doesn't match, FLASH programming is rejected and a warning i...
Arm Cortex: JTAG scan when multiple devices are connected in a chain 15-Sep-2026
JTAG Chain scan functionality enables you to define IR/DR Prefix/Postfix values which could be entered in Hardware |CPU Options |JTAG . That is important when several devices are connected in a chain and you want to debug for example the second one. Possible solution From winIDEA build 9.2...
Infineon TriCore: Synchronizing multiple cores 15-Sep-2026
Multiple cores are hardware-wise not synchronized by default after reset. Possible solutions Enabling multi-core synchronization 1. Enable the option S ynchronize selected cores (stop/run) when possible in Hardware |CPU Options |Debugging. 2. Enable synchronization in Hardware |CPU Options...
winIDEA: Infineon AURIX – Prevent locking 15-Sep-2026
AURIX devices have several sensitive modules/areas (BMHDs, HSM, UCBs), which could lock the device permanently when configured incorrectly. To prevent locking your device follow these recommendations: Image checker Use theImage checker during UCB or HSM code programming. A separate license...
NXP S32K31x: Trace recording is incomplete and it shows synchronization errors 15-Sep-2026
Trace recording is incomplete because of the big gaps in time and trace message number, with ITM Synchronization lost messages in between.This typically happens due to the SWO clock instability, or too high of SWO data rate. Possible solution 1. Update to the latest winIDEA version . 2. Ad...
Buffer (FIFO) overflows 15-Sep-2026
In some cases, the CPU is not able to stream the trace data quickly enough, which results in overflow errors. Errors are displayed in the Analyzer Output window and indicated in theTrace window with brown colored lines. Possible solutions Limit the scope of the recorded variables (e.g. tas...
Arm Cortex: The application does not stop after reset 15-Sep-2026
Possible solution Verify the RESET method selection in the Hardware |CPU Options |Reset. Explanation On Cortex devices internal reset logic can be implemented in various ways. The debug tool must be aware of the reset logic implementation to connect to the target microcontroller and gain c...
Arm Cortex-M: System reset fails 15-Sep-2026
System reset or download (Error 258) fails on XMC1000 and NXP LPC family devices, when the debugger uses the reset vector catch mechanism to stop the CPU after the CPU reset release. Possible solution Always leave the CORERESET exception unchecked. 1. Open Hardware | CPU Options | CORE0 . ...