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RTOS in undefined state 15-May-2025
After a Download or Reset, RTOS objects may initially be in an undefined state. This is indicated by the message: RTOS in undefined state displayed across all related windows. Solution Once the current task is set, the windows should display associated content, and the message should no lo...
Can not access rcX RTOS state 15-May-2025
When memory is not accessible, all windows will display the message: Cannot access RTOS state This is expected behavior until a debug session with download is initiated. If the message persists after the download has started, it likely means that the RTOS object symbols cannot be evaluated...
Arm Cortex NXP LPC15xx: SWO trace 07-May-2025
On LPC15xx devices, you can configure I/O pin to use for a SWO trace with a custom initialization script. Environment will remap the selected pin to output SWO trace, disabling any function previously assigned by the application. Possible solution 1.Add the custom script LPC15xx_TraceInit....
Arm Cortex NXP LPC1xxx: Read protection (CRP) area at 0x2FC 07-May-2025
Code Read Protection (CRP) is a mechanism that allows you to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in Flash location at 0x000002FC. If value 0...
Arm Cortex NXP LPC13xx: Startup 07-May-2025
The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code, or, in the case of the LPC13xx, it can obtain the boot image as an attached MSC device through USB. A LOW level during reset at pin PIO...
Arm Cortex NXP LPC435x: Startup 07-May-2025
Per LPC435x specification, Cortex-M0 is not accessible through the SWD debug interface. It’s accessible only through the JTAG debug interface. It’s recommended to use the JTAG debug interface when debugging LPC435x, which allows debugging both Cortex-M4 and Cortex-M0 cores . If only the SW...
Arm Cortex NXP LPC: Internal Flash Programming 06-May-2025
The debugger programs the code directly into the internal Flash memory through the standard Debug Download and based on the selected CPU: Identifies which code from the download file fits into the internal Flash. Loads it to the Flashthrough the flash programming procedure. The Flash progr...
Arm Cortex Microchip ATSAML1x: Chip Erase 06-May-2025
The Chip Erase script removes the security on the chip (if not permanently secured). The script is executed manually. In cases where the device is secured or possibly a malfunctioning application is loaded on it, the Chip Erase command allows to erase memories of the device and provides se...
Arm Cortex Cypress Traveo II: Supervisory Flash (SFLASH) 06-May-2025
Programming of Supervisory Flash is divided into two types of programming: User rows (available in VIRGIN and NORMAL state of SoC) Cypress rows (available only in the VIRGIN state of SoC) To troubleshoot possible issues with Cypress Traveo II use logging via Help | Support | Log. Enable ac...
How to reach maximum Flash programming performance? 06-May-2025
Programming applications to a microcontroller can take a lot of time, especially if the application is large, the storage device is external memory and the data rate is slow. Possible solutions Minimize download time - general settings Check the frequency of the debug interface and set up ...