Below example is presented on the Microchip MCP4921 ADC chip.
1. Select ADIO digital output pins as a part of certain digital bank in output mode for SPI clock, CS and Data pins, and save the settings.
2. Perform a Debug Download in Debug | Download.
3. Select a new certain pattern in Hardware | FNet Options | <ADIO> | DIO1 | Pattern.
4. In the Pattern generator perform the following for each active SPI pin.
The frame message has control value 0x5 and data value 0x7DA for the SPI message. The SPI clock is 500 kHz. The channels are defined in the following order: SPI_CS, SPI_CLK and SPI_DATA.
The pattern for the single SPI message with delay after the SPI message is:
100,1;000,1;x1x,1;x00,1;x1x,1;x01,1; x1x,1;x00,1; x1x,1; x01,1; x1x,1;x01,1; x1x,1; x00,1; x1x,1;x01,1; x1x,1; x01,1; x1x,1;x01,1; x1x,1; x01,1; x1x,1;x01,1; x1x,1; x00,1; x1x,1;x01,1; x1x,1; x00,1; x1x,1;x01,1; x1x,1; x00,1; x1x,1;x00,1; 1xx,100;
For a detailed visual presentation refer to Webinar – testIDEA: Test Use-Cases including real Hardware Signals.