Arm Cortex NXP LPC13xx Startup

The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code, or, in the case of the LPC13xx, it can obtain the boot image as an attached MSC device through USB.

A LOW level during reset at pin PIO0_1 is considered an external hardware request to start the ISP command handler or the USB device enumeration without first checking for a valid user code. The state of PIO0_3 determines whether the UART or USB interface will be used (refer to the CPU user manual for more details).

Assuming that power supply pins are at their nominal levels when the rising edge on RESET pin is generated, it may take up to 3 ms before PIO0_1 is sampled and the decision on whether to continue with user code or ISP handler/USB is made.

• If PIO0_1 is sampled low and the watchdog overflow flag is set, the external hardware request to start the ISP command handler is ignored.
• If there is no request for the ISP command handler execution (PIO0_1 is sampled HIGH after reset), a search is made for a valid user program. 
• If a valid user program is found then the execution control is transferred to it.
• If a valid user program is not found, the auto-baud routine is invoked.

Pin PIO0_1 is used as a hardware request signal for ISP UART/USB and requires special attention. Since PIO0_1 is in high impedance mode after reset, it is important that the user provides external hardware (a pull-up resistor or other device) to put the pin in a defined state. Otherwise, an unintended entry into ISP mode may occur.

The criterion for valid user code

The reserved Cortex-M exception vector location 7 (offset 0x 001C in the vector table) should contain the 2’s complement of the check-sum of table entries 0 through 6.

This causes the checksum of the first 8 table entries to be 0. The boot loader code checksums the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is transferred to the user code.

If the signature is not valid, the auto-baud routine synchronizes with the host via serial port 0 or boots from the USB port (PIO0_3 is sampled high).

Watchdog

A regular Reset cannot be used with LPC devices.  This results in a short-core run before it is stopped. At that time the watchdog might be enabled. It remains counting in stop mode and it is only disabled on external reset or overflow reset.

Another external reset cannot be used – it would cause an endless loop. Instead, the watchdog status is checked after each reset. If the watchdog is enabled the debug session is paused until the overflow reset is detected. Since the core is set to stop on reset the debug initialization can continue.

More resources in winIDEA Help

• Reset
• Watchdog issues