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Arm Cortex
Arm Cortex / Traveo II: Stop the secondary cores immediately after Reset 29-Nov-2024
After issuing a Resetin winIDEA, the primary core (Cortex-M0+) is stopped at the reset vector, while the secondary core(s) are IDLE (Debug status IDLE will be shown). The secondary core(s) are then started by the application running on the primary core. Configuring Hardware |CPU Options |C...
Arm Cortex AMD Zynq: JTAG Chain 28-Nov-2024
The JTAG chain is configurable within Zynq SoC. Cascaded JTAG works with an empty device. You must provide a soft core to connect external pins to Arm DAP if Independent JTAG mode is desired. Refer to Mode Pin Settings and JTAG and DAP Subsystem chapters in the Zynq reference manual for mo...
Arm Cortex NXP Kinetis: Configuring trace ports 28-Nov-2024
Kinetis devices encompass a range of models, each offering different levels of Embedded Trace Macrocell (ETM) capabilities and parallel trace output pins. To determine the specific features available on your target device, please consult the corresponding reference manual. Affected familie...
Arm Cortex: L1 cache Write-through 28-Nov-2024
In general, for a real-time observation of the variables these must be written in the data memory and not, for example, only held in the cache, since cache memory is not visible to the debugger. If you want the "cached only" variables to be seen by the debugger, you will need an EVE script...
Arm Cortex Cypress Traveo II: Emulation Adapters 28-Nov-2024
Cypress Traveo II packages (64-pin, 80-pin, 100-pin, and 144-pin) have different trace capabilities. The following Emulation Adapters provide the trace interfaces, where a trace port is not available or lacks the full trace capability: CYT2B9 CYT2B7 CYT2BL By default, port pins P18 (P18_3 ...
NXP S32K31x: Trace recording is incomplete and it shows synchronization errors 26-Nov-2024
Trace recording is incomplete because of the big gaps in time and trace message number, with ITM Synchronization lost messages in between.This typically happens due to the SWO clock instability, or too high of SWO data rate. Possible solution 1. Update to the latest winIDEA version . 2. Ad...
Arm Cortex-M: Locked/secured device 18-Nov-2024
Possible solution 1. Select Debug |Prepare to Attach . 2. If using Hot Attach, follow the Hot Attach procedure to safely attach to the Target. 3. Select Hardware |Scripts |Unsecure (can also be Chip Erase or similar). This operation needs JTAG/SWD debug port to be accessible. Devices, wher...
Arm Cortex: The application does not stop after reset 12-Nov-2024
Possible solution Verify the RESET method selection in the Hardware |CPU Options |Reset. Explanation On Cortex devices internal reset logic can be implemented in various ways. The debug tool must be aware of the reset logic implementation to connect to the target microcontroller and gain c...
Arm Cortex-A: Memory window shows inaccessible memory incorrectly in virtual memory area 06-Nov-2024
When using the winIDEA Memory window to view memory that should be inaccessible, you may notice a discrepancy in the memory display between the Virtual and IPmemory areas. Specifically, the Virtualmemory area displays "00" values instead of the expected "??," while the IP memory area corre...
RCAR-S4 configuration for Renesas evaluation board 06-Nov-2024
RCAR-S4 consists of Arm Cortex and G4MH cores. If you use an evaluation board you have to use different debug connectors and change some switches. Configure evaluation board The evaluation board has 2 debug connectors, for Cortex and G4MH cores. Make sure you use the correct debug adapter ...
Arm Cortex-M: System reset fails 06-Nov-2024
System reset or download (Error 258) fails on XMC1000 and NXP LPC family devices, when the debugger uses the reset vector catch mechanism to stop the CPU after the CPU reset release. Possible solution Always leave the CORERESET exception unchecked. 1. Open Hardware | CPU Options | CORE0 . ...
Arm Cortex / Texas Instruments AWR Family: Download to Local RAM fails 06-Nov-2024
When debugging a Texas Instruments AWR family device, it is possible that the RAM download after a reset/power cycle fails. Possible solution A soft reset is needed. Use the SoftResetCR4 script . More resources inwinIDEA Help Arm Cortex architecture-specific notes
NXP S32R294: Non-secure boot 22-Oct-2024
There are various ways to boot the NXP S32R294 in non-secure mode depending on the development stage of your project. The how-to guide below provides solutions for different examples. Solution Refer to NXP S32R294: Non-secure boot in winIDEA Help. More resources in winIDEA Help How to prog...
Arm Cortex Texas Instruments Jacinto/Sitara: Configuring Memory area (bus) 19-Oct-2024
For SoCs (e.g. AM24xx, AM64xx, AM26xx) with multiple cores organized into clusters, you must manually select the memory area (bus) to successfully perform Debug | Download . Possible solution Specify Memory area (bus) 1. Open Debug |Configure Session |SoCs |Program Files |Program File . 2...
JTAG scan when multiple devices are connected in a chain 19-Oct-2024
JTAG Chain scan functionality enables you to define IR/DR Prefix/Postfix values which could be entered in Hardware |CPU Options |JTAG . That is important when several devices are connected in a chain and you want to debug for example the second one. Possible solution From winIDEA build 9.2...
ArmCortex / STM32: ST-Link debug session fails 19-Oct-2024
Possible causes Emulation start failed Instable connection Download not working UMI errors Write to Memory Window fails or memory read fails Solution Upgrade ST-Link firmware using ST firmware upgrade tool.
Arm Cortex-M: Target is in STOP-VCATCH after reset 11-Sep-2024
When the CPU executes a (watchdog) reset, it triggers a CORERESET exception. By default, the debugger is set to catch such an exception and halts the CPU, which is indicated by the STOP-VCATCH Debug status. Possible solution 1. Open Hardware | CPU Options | Cores . 2. Make sure CORERESET i...
Arm Cortex AMD Zynq UltraScale+: DDR RAM Initialization 09-Aug-2024
To download and run an application in DDR RAM on AMD Zynq UltraScale+ using winIDEA, refer to Initialize AMD Zynq UltraScale+ DDR RAM how-to guide. More resources Add a custom initialization script
Arm Cortex Cypress Traveo II: Initialize Debug session via EVE script parameter 09-Aug-2024
winIDEA enables an alternate debug session initialization if issues with downloading occur. This only affects download operations. Possible solution 1. Add the custom initialization script to Hardware | CPU Options | Reset | Initialization before programming | Connect . 2. Select Yes in th...
Arm Cortex NXP LPC: Internal Flash Programming 09-Aug-2024
The debugger programs the code directly into the internal Flash memory through the standard Debug Download and based on the selected CPU: Identifies which code from the download file fits into the internal Flash. Loads it to the Flashthrough the flash programming procedure. The Flash progr...
Arm Cortex Texas Instruments TMS570LC4357: Trace Triggers 07-Aug-2024
Specific settings should be configured for this device so the trace trigger works correctly. Possible solution 1. Open Hardware | CPU Options | CTM/CTI . 2. Check in CTM Channel 2: R5.0˜ETMTRIGGER in TRIGINs. TPIUTRIGIN in TRIGOUTs . More resources in winIDEA Help CTM/CTI
Arm Cortex NXP LPC: LPC11A02/04 Debug Pin Remapping in Boot 07-Aug-2024
For WLCSP packages, the boot loader changes the default pin configuration to: PIO0_2 register - SWCLK PIO0_3 register - SWDIO TCK_PIO0_5 register - PIO0_5 SWDIO_PIO0_10 register -PIO0_10 Possible solution Connect PIO0_2 and PIO0_3 to the debug connector for debugging. More resources in win...
Arm Cortex NXP LPC1xxx: Read protection (CRP) area at 0x2FC 07-Aug-2024
Code Read Protection (CRP) is a mechanism that allows you to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in Flash location at 0x000002FC. If value 0...
NXP/ST Power Architecture Stellar SR6P6 and SR6P7/G7: JTAG Password to unlock debug interface with JTAG Password 06-Aug-2024
Possible solution 1. Open Hardware |CPU Options |Reset. 2. Add a custom EVE script Connect To SoC Using TnDCM Reset to I nitialization before Programming | Connect . 3. Check the Same as Programming in Initialization before Debug Session section. 4. Edit the script parameters via the arrow...
Arm Cortex STM32H7: Flash Configuration 05-Aug-2024
Microcontrollers of the STMicroelectronics STM32H7 family have a special Flash Configuration Field where different settings for Flash programming can be adjusted. Possible solution 1. Open Hardware | device | Configure | FLAGS Configuration . 2. Configure according to your use case: Parall...
Arm Cortex Microchip ATSAML1x: Chip Erase 05-Aug-2024
The Chip Erase script removes the security on the chip (if not permanently secured). The script is executed manually. In cases where the device is secured or possibly a malfunctioning application is loaded on it, the Chip Erase command allows to erase memories of the device and provides se...
Arm Cortex Cypress Traveo II: Debug session initialization prerequisites 05-Aug-2024
Traveo II devices require a debug interface operating at a frequency higher than 1500 kHz. This permits the debugger to execute the necessary debug initialization procedures fast enough and within the device start-up time window constraint after the CPU reset line is released by the BlueBo...
Arm Cortex / Cypress Traveo II: Freeze peripherals during debug halt 05-Aug-2024
The peripherals on Traveo II devices, such as timers, are not frozen by default when the device is halted in debugging. CYT4DN CYT4BF CYT4BB CYT3DL CYT3BB CYT2BL CYT2B9 CYT2B7 CYT2B6 Possible solution Custominitialization scripts are distributed with winIDEA to freeze the Traveo's peripher...
NXP S32G2/3xx/S32R45x/S32K3: Unlock secure debug 02-Aug-2024
Password and Challenge/Response authentication are secure debug modes that prevent unauthorized access to the SoC by requiring correct credentials at the start of a debug session. Once authenticated, the SoC remains unsecured until a power-on-reset or similar reset occurs. For Password aut...
NXP S32K3xx: Debug password and endianness 02-Aug-2024
While using winIDEA you encounter an error related to debug password configuration, e.g. Debug access failed . Possible solutions Verify endianness It's possible that the endianness of the provided password is incorrect. For example, if you programmed the password into UTEST as 0x00, 0x01,...
NXP S32G2xx/S32G3xx/S32R4x: Attach and Detach workaround 02-Aug-2024
Additional configuration is required when using Attach/Detach procedure in conjunction with the workaround proposed to the M7 application core hung state erratum (ERR051149). Refer to the NXP errata documentation for a more detailed description and the proposed workaround. Solution Perform...
Arm Cortex-M LPC4357: Debugging M4 core via SWD Debug Protocol 01-Aug-2024
The LPC4357 is a dual-core with ARM Cortex-M4 and Cortex-M0 cores, which are accessed via the following Debug Protocols: Cortex-M4 on JTAG and SWD Cortex-M0 only on JTAG By default winIDEA tries to connect to all available cores. When selecting the SWD Debug Protocol, winIDEA should connec...
Arm Cortex-M Cypress Traveo II 2M VIRGIN devices: Fail to establish debug session 01-Aug-2024
Debug session with Cypress Traveo II VIRGIN (life cycle) devices will be established partially - the core will not be stopped at the start of your application. Debugging VIRGIN devices is not supported from winIDEA 9.21.29. To inspect if you have a VIRGIN device refer to topic Reset and Fl...
Arm Cortex Cypress S70FS01GS: Sector Map Configuration 01-Aug-2024
Cypress S70FS01GS Flash non-volatile memory device implements JEDEC standard supporting Serial Flash Discoverable Parameters (SFDP). However, the S70FS01GS device is a dual die stack of two FS512S dies with consecutive memory addresses and prior to the first use initial formatting is requi...
Arm Cortex-M: Failed to initialize debug session 01-Aug-2024
Possible solutions LPC devices The most common cause is that the image programmed in the Flash prevents any further debug access or connections and fails to establish a debug session. The image usually contains code that: Sets the SoC clocks up incorrectly Enables a watchdog timer This put...
Arm Cortex Texas Instruments AWR18xx/68xx: Soft Reset 01-Aug-2024
For Texas Instruments AWR18xx and AWR68xx devices, the ROM must be eclipsed with the RAM content after the bootloader. This process requires manual enabling of ROM eclipsing, followed by a soft reset. Possible solution 1. Select Hardware | Scripts | SoftResetCR4 . 2. Retry Download once th...
Arm Cortex NXP LPC13xx Startup 01-Aug-2024
The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code, or, in the case of the LPC13xx, it can obtain the boot image as an attached MSC device through USB. A LOW level during reset at pin PIO...
Arm Cortex NXP LPC435x: Startup 01-Aug-2024
Per LPC435x specification, Cortex-M0 is not accessible through the SWD debug interface. It’s accessible only through the JTAG debug interface. It’s recommended to use the JTAG debug interface when debugging LPC435x, which allows debugging both Cortex-M4 and Cortex-M0 cores . If only the SW...
Arm Cortex-M NXP LPC: Boot and Memory Remapping 01-Aug-2024
On Cortex-M devices from the LPC family a Boot Rom is present with: Code that is executed on reset A memory mapping register (MEMMAP, SYSMEMREMAP) After the debug connection is established: The target core is released from reset and stopped at the beginning of the boot code. The initial st...
Arm Cortex NXP Kinetis K2x/EA: Flash configuration 31-Jul-2024
Kinetis K2x The NXP Kinetis K2x series microcontrollers contain a 16-byte flash configuration field within the program flash memory. This field is essential as it stores default protection settings (loaded on reset) and security information, enabling the MCU to restrict access to the flash...
Arm Cortex NXP LPC15xx: SWO trace 31-Jul-2024
On LPC15xx devices you can configure I/O pin to use for a SWO trace with a custom initialization script. Environment will remap the selected pin to output SWO trace, disabling any function previously assigned by the application. Possible solution 1.Add the custom script LPC15xx_TraceInit.c...
Arm Cortex: How to configure general CPU settings? 31-Jul-2024
These configuration steps arerequired to connect BlueBox to the Target andperform a CPU Reset, which establishes the initial Debug connection. Solution 1. Create a New Workspace via File | Workspace | New Workspace . 2. Open Hardware | CPU Options | SoC: a. Select JTAG or SWD under the Deb...
NXP S32E/S32G/S32R/S32Z: Cold Start 31-Jul-2024
These topics describe how to start debugging the Arm Cortex-M7 and A53 / Arm Cortex-M33 or Cortex-R52 cores if no valid boot image is found on: Cold Start with NXP S32G/S32R Arm Cortex-M7 or A53 core Cold Start with NXP S32E2/Z2 Arm Cortex-M7 or A53 core
Failed to initialize debug session / Emulation start failed 30-Jul-2024
The error means that the debugger failed to connect to the target CPU. This can be for different reasons. When troubleshooting the initial debug connection to the target CPU, it is recommended to use the CPU Reset instead of Download. Possible causes and solutions BlueBox is not properly c...
Arm Cortex Texas Instruments TMS570: ECC functionality 30-Jul-2024
Flash on TMS570 devices features an ECC functionality. The ECC area can be programmed automatically with values corresponding to downloaded data or you can provide your own ECC download data. The option for automatic ECC generation is located in Hardware | TI TMS570 | Configure | FLAGS Con...
Arm Cortex Texas Instruments CC2650: SWO pin configuration 30-Jul-2024
CC265xx devices support configuring the DIO pin on which the Serial Wire Output (SWO) trace is output. Possible solution 1. SWO output must be connected to the TDO pin of the Arm adapter. 2. Select cJTAG Debug Protocol in Hardware | CPU Options | SoC . Since the JTAG protocol uses TDO for ...
Arm Cortex Infineon XMC: Halt On Reset 29-Jul-2024
XMC devices implement a special functionality for stopping the CPU at the reset vector after reset when the debugger is connected. Possible solution 1. Go to Hardware | CPU Options | Reset | Reset pin. 2. Select the Regular Reset method. More resources in winIDEA Help Reset
Arm Cortex NXP LPC17xx: Startup 29-Jul-2024
The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code. A LOW level after reset at pin P2.10 is considered an external hardware request to start the ISP command handler. Assuming that power s...
Arm Cortex Microsemi SmartFusion2: Handling flash write threshold errors 18-Jul-2024
SmartFusion2 devices have threshold detection for the number of writes performed on flash memory. When this threshold is reached flash programming API returns an error status. Possible solution 1. Open Hardware | device | Configure | FLAGS Configuration . 2. Select IgnoreWriteThresholdErro...
NXP S32G/S32R/S32S: eFuse programming 16-Jul-2024
eFuses are OTP (One-Time Programmable) memory and can be used for several purposes.These how-to guides describe how to read or write eFuses using Python script on: NXP S32G/S32R NXP S32S Technical Note for NXP S32S includes confidential information and NDA with the silicon vendor is requir...
Arm Cortex-M: Error 304: Check Debug Adapter 10-Jun-2024
Error 304 means the BlueBox fails to connect and establish debug session with theCortex-M-basedtarget CPU. Possible solutions Use the Reset debug command When troubleshooting the initial debug connection to the target CPU, it's recommended to use the CPU Reset debug command instead of the ...
Arm Cortex: Debugging i.MX 8QuadMax M4 Processor 15-Mar-2024
You can debug i.MX 8QuadMax M4 Processor cores using boot image where all application cores are booted and using boot image where only M4_0 core is booted. More information in winIDEA Help How-to guide Debugging i.MX 8QuadMax M4 Processor .
NXP S32K: JTAG Lock procedure on S32K1xx devices 14-Mar-2024
The program flash memory on S32K1xx devices contains a specific region that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFC module. This topic describes how to allow programming in winIDEA in this region that ...