Arm Cortex Cypress Traveo II: L1 cache Write-through

In general, for a real-time observation of the variables these must be written in the data memory and not for example only held in the cache since cache memory is not visible to the debugger. If you want the "cached only" variables to be seen by the debugger, use the provided L1 Cache Write-through enable EVE script, which configures the microcontroller to propagate writes of variables cached in the L1 cache also to the memory. 

The script sets the FORCEWT bit of the CM7_CACR register. The debugger has no access to the contents of the cache memory, the only way to observe its contents by debugger is by forcing it to write through any changes directly from the cache memory to the SRAM locations, which are accessible by the debugger.

The example below shows how variables are seen to the debugger in the memory:

Solution

Execute Hardware | Scripts | Enable CacheWriteThrough. 

Do note that its effect is reset if the microcontroller goes through any kind of a reset and the variables being cached only will no longer be visible in the real-time Watch Window.