Arm Cortex: L1 cache Write-through

In general, for a real-time observation of the variables these must be written in the data memory and not for example only held in the cache since cache memory is not visible to the debugger. If you want the "cached only" variables to be seen by the debugger, you will need an EVE script or an INI file to enable L1 Cache Write-through. This configures the microcontroller to propagate writes of variables cached in the L1 cache also to the memory.

The debugger has no access to the contents of the cache memory, the only way to observe its contents by debugger is by forcing it to write through any changes directly from the cache memory to the SRAM locations, which are accessible by the debugger.

The example below shows how variables are seen to the debugger in the memory:

Solutions

Provided EVE script (Cypress Traveo II)

This solution is specific to Cypress Traveo II devices. You can use the provided EVE script to enable L1 Cache Write-through. The script sets the FORCEWT bit of the CM7_CACR register. 

Execute Hardware | Scripts | Enable CacheWriteThrough. 

Custom INI file (Any Cortex M7 device)

You must create a new INI file to enable L1 Cache Write-through, which sets the FORCEWT bit of the CM7_CACR register, and manually add it to winIDEA. 

1. Create an Enable_L1_Cache_WriteThrough.ini file and copy it into your winIDEA Workspace folder. 

2. Go to Hardware | CPU Options | Reset |  Initialization before programming | Initialize.

3. Select Custom in the dropdown menu.

4. Click on the arrow button and select Add from workspace folder. Select the INI file.

5. Go back to Hardware | CPU Options | Reset and carry out the following:

• Disable Reset CPU after download (Invalidates initialization)
• Enable Initialization before Debug session | Initialize | Same as Programming
• Enable Initialization at Attach | Initialize | Same as Debug

More resources in winIDEA Help

• Reset
• Initialization Sequence