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Solution To disable ENDINIT protection and be able to change the registers, add this line to any initialization file: A CBS_OCNTRL L 0x000000C0 // Disable ENDINIT More resources in winIDEA Help Initialization sequence Internal Flash programming
The FNet Bridge Multi SoC synchronization enables the coordination of two separate BlueBox Debuggers via the FNet communication network. This setup facilitates synchronous debugging and tracing across multiple systems, achieving low latency synchronization typically within a few microsecon...
Since Aurix is a highly security-oriented device, it is by default not possible to apply the debug password at any time, but rather only in a very short period of time after a Power on, Application or System reset. This fact is very important when dealing with Application and System resets...
With the TriCore plugin core window Counters, y ou can measure the time between two functions, e.g. Type_Simple which starts counters, and Type_Enum which stops counters. Solution Refer to the how-to guide in winIDEA Help.
Programming User Configuration Block ( UCB ) memory is essential otherwise the CPU does not have the information from which address to boot. Refer to the Infineon documentation to determine which UCB sectors need to be programmed. The number of writes to UCB is limited. Refer to your TriCo...
The error means that the debugger failed to connect to the target CPU. This can be for different reasons. When troubleshooting the initial debug connection to the target CPU, it is recommended to use the CPU Reset instead of Download. Possible causes and solutions BlueBox is not properly c...
First check, whether your CPU supports trace - refer to the topic Trace is not licensed . Possiblesolutions Trace Buffer is configured in Hardware | CPU Options | SoC. Default The option Use all available memory for trace buffer should work in most cases assuming that complete TCM memory i...
DAP over CAN Physical Layer Converter (DXCPL) enables debugging via the regular CAN pins of the ECU connector without opening its housing. This connection is electrically robust due to the nature of the CAN bus. The DXCPL Converter translates Infineon AURIX™ SPD (Single Pin DAP) encoded DA...
TriCore architecturally does not have a mechanism that would allow the CPU to be stopped when a trap (in some other architectures known as an exception) occurs.Various mechanisms can trigger traps on the core, such as null pointer dereference or data alignment errors. Possible solutions Sc...
By default, Data Flash (DFLASH), which is divided into two banks DFLASH0 and DFLASH1, is programmed through the regular debug download (fast flash programming based on flash programming monitor) via Hardware | Infineon device | Configure. DFLASH can be split and used separately by the user...
Aurix devices have several sensitive modules/areas (BMHDs, HSM, UCBs), which could lock the device permanently when configured incorrectly. To prevent locking your device follow these recommendations: Image checker Use theImage checker during UCB or HSM code programming. A separate license...
Multiple cores are hardware-wise not synchronized by default after reset. Possible solutions Enabling multi-core synchronization 1. Enable option S ynchronize selected cores (stop/run) when possiblein Hardware |CPU Options |Debugging. 2. Option Synchronize this core option in Hardware |CPU...
After trying to flash your device winIDEA displays the following error message: License error 15: These licenses are not present on FNet_1 - TC1xx/TC2xx. Possible solutions Proper debug licence is required Check if you are using or have purchased a suitable license for your device. For exa...
When the Aurix is reset with the debugger connected and the Hardware Security Module (HSM) is enabled in the User Configuration Block (UCB), the boot code of TC2xx / TC3xx sets a breakpoint to HSM’s first instruction. This stops the HSM core from running and if the primary core expects the...
The UCB Flash must be writable to configure the debug password protection. Using this procedure you may lock the device! Possible solution 1. Configure winIDEA to use a password via Hardware | CPU Options | SoC. 2. S et a password. Refer to the winIDEA Help Password protection chapter for ...
When Aurix devices are in the debug mode, W atchdog is by default enabled, but the Watchdog Timer is unconditionally suspended (stopped), which means that the Watchdog never resets the chip. To use the Watchdog during debugging, you have to disable the Watchdog Timer suspended logic (or en...
Possible issues Variable is changing, but Real-time Memory access still shows the initial value. In this case, the variable may be cached, which makes Real-time Memory access impossible. Variable value is not updated in the Watch and Memory windows Note that using any of these solutions ma...
Error message AGBT FIFO overflow indicates that TriCore’s internal FIFO overflowed, which means that in a short period of time too many trace messages were written into FIFO. Below steps explain on the TC3xx example how to define custom triggers and use an algorithmic approach to find two ...
Possible causes: Faulty hardware: Target, Debug Adapter, or Active Probe CPU is always in reset or the debugger cannot reset the CPU Bad contact if the CPU is in a socket External watchdog resets the chip periodically DAP Wide mode is selected in Hardware |CPU Options |SoC , however, only ...
These configuration steps are required to connect BlueBox to the Target and perform a CPU Reset, which establishes an initial Debug connection. Solution 1. Create a new winIDEA Workspace via File |Select Workspace. 2. Open Hardware |CPU Options |SoC . 3.Select JTAG, DAP Standard, DAP Wide,...
How to avoid unneeded issues with peripheral devices when debugging the application? Possible solutions Suspend peripherals while stopped Use the Hardware / CPU Options / Reset / At Initialization /Suspend peripherals while stopped option and select the peripheral functions you want to be ...
Hot Attach functionality allows you to attach the BlueBox development system to a running target system without affecting its operation and have all debug functions available. Refer to the winIDEA Help Hot Attach chapter for more information.
This topic applies only to winIDEA versions up to 9.21.126 . For HSM flash sector security in newer winIDEA versions the code which goes to those sectors is already checked by the Image checker. For more information refer to the Infineon Aurix: Prevent locking . On the first generation, Tr...
The HSM (Hardware Security Module) is an optional module available on selected Aurix devices. Through winIDEA, you can program an HSM application and configure the UCB (User Configuration Block) which is required to enable the HSM on your Aurixdevice. More information in winIDEA Help: TC2x...
Filling the whole block of memory with any value using function Fill Memory in the Memory Window in order to clear UCB section of Aurix devices will LOCK the chip. More resources in winIDEA Help Storage programming Memory window
Error message AGBT FIFO overflow indicates that TriCore’s internal FIFO overflowed, which means that in a short period of time too many trace messages were written into FIFO. Below steps explain on the TC3xx example how to define custom triggers, use algorithmic approach, halving the range...
Solution 1. Suspend the peripheral module in the winIDEA initialization file by uncommenting lines: Example: //----------------------- //GTM suspend control A GTM_CLC L 0x00000000 A GTM_OCS L 0x12000000 //----------------------- STM (System Timer Module) is suspended by default. 2. Enable ...
Debugging (step in, step over...) a target application is working until the StartOS function is called. This function initializes the System timer (STM). On TC3xx devices usually that is the STM0 timer. The timer is used by the scheduler to switch between the tasks. If you want to debug su...
winIDEA supports SOTA (Software Over The Air) solution for Infineon Aurix 2nd generation TC3xx devices. Possible solutions Before configuring the SOTA mechanism on your chip, it is essential to read and understand the Infineon-related documentation and details about the content of the UCB_...
Standby Controller (SCR) is an 8-bit microcontroller that can continue to run during standby mode. It is based on the XC800 Core which is compatible with the industry standard 8051 processor and is available on selected TC3xxx devices. SCR core is selectable in winIDEA as any other core. S...
This topic visualisessteps how to define custom triggers and use an algorithmic approach to find two or more problematic functions that generate too many trace messages in a wider range which are described in the topic How to find two or more problematic functions in a wider range if AGBT ...
On-Chip trace logic monitors the CPU execution inside the SoC. O btained data is compressed using trace protocols and: Streamed out through the trace port, where BlueBox debugger is capturing the data on the trace port. Each sample is time stamped by the BlueBox timer OR Captured in the in...