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Programming
UMI errors in winIDEA 25-Sep-2025
UMI (Universal Monitor Interface) is a proprietary interface that allows winIDEA a flexible and efficient way of communication with an embedded application called the UMI monitor. The design of UMI allows the development team to support any new type of SoC of storage device in a very short...
Flash programming with multiple Program Files 17-Sep-2025
This topic explains the process of programming multiple Program Files using winIDEA, and particularly focuses on creating memory images and handling overlapping files. When downloading files, winIDEA creates a single memory image that encompasses all the files to be programmed onto the tar...
Arm Cortex Texas Instruments Jacinto/Sitara: Configure Memory area (bus) 09-Sep-2025
For SoCs (e.g., AM24xx, AM64xx, AM26xx) with multiple cores organized into clusters, you must manually select the memory area (bus) to successfully perform Debug | Download . Possible solution Specify Memory area (bus) 1. Open Debug |Configure Session |SoCs |Program Files |Program File . ...
Arm Cortex Cypress S70FS01GS: Configure Sector Map 09-Sep-2025
Cypress S70FS01GS Flash non-volatile memory device implements JEDEC standard supporting Serial Flash Discoverable Parameters (SFDP). However, the S70FS01GS device is a dual die stack of two FS512S dies with consecutive memory addresses, and prior to the first use, initial formatting is req...
Infineon AURIX: Managing CONFIRMED UCBs 25-Jul-2025
Infineon AURIX SoCs feature UCBs, which are used as a configuration data storage. The configuration is applied by the Startup Software (SSW) on reset. UCBs are usually either in: UNLOCKED state - Can be read normally by any bus master. CONFIRMED state - Can prevent read and write access, a...
Renesas RH850: Using ICUM as a boot core and unable to download 23-Jul-2025
When the ICUM is enabled flash erase and program operations are not possible. ICUM-protected setup requires a custom procedure to perform a download. Note that disabling and re-enabling the ICUM is not necessary if a download files' image is unchanged. Python scripts are available per requ...
Renesas RH850/U2x: Security Settings Area programming 10-Jul-2025
This Technical Note describes how to program the Security Setting Area (SSA) on RH850/U2x devices via Python scripts. Please send a request to the Support team ! This Technical Note includes confidential information and an NDA with the silicon vendor is required.
NXP/ST Power Architecture / ST SPC58: Flash mass erase on HSM enabled device 10-Jul-2025
When Alternate Flash Programming Interface is set, only the HSM core has access to HSM code and data flash. Erased HSM code flash does not contain valid HSM boot headers, therefore HSM core remains in reset state forever, and flash monitor cannot be executed there. As a consequence the HSM...
Arm Cortex NXP LPC: Internal Flash Programming 06-May-2025
The debugger programs the code directly into the internal Flash memory through the standard Debug Download and based on the selected CPU: Identifies which code from the download file fits into the internal Flash. Loads it to the Flashthrough the flash programming procedure. The Flash progr...
Arm Cortex Microchip ATSAML1x: Chip Erase 06-May-2025
The Chip Erase script removes the security on the chip (if not permanently secured). The script is executed manually. In cases where the device is secured or possibly a malfunctioning application is loaded on it, the Chip Erase command allows to erase memories of the device and provides se...
Arm Cortex Cypress Traveo II: Supervisory Flash (SFLASH) 06-May-2025
Programming of Supervisory Flash is divided into two types of programming: User rows (available in VIRGIN and NORMAL state of SoC) Cypress rows (available only in the VIRGIN state of SoC) To troubleshoot possible issues with Cypress Traveo II use logging via Help | Support | Log. Enable ac...
How to reach maximum Flash programming performance? 06-May-2025
Programming applications to a microcontroller can take a lot of time, especially if the application is large, the storage device is external memory and the data rate is slow. Possible solutions Minimize download time - general settings Check the frequency of the debug interface and set up ...
Arm Cortex Stellar SR6P6 and SR6P7/G7: JTAG Password to unlock debug interface 18-Apr-2025
Possible solution 1. Open Hardware |CPU Options |Reset. 2. Add a custom EVE script to I nitialization before Programming | Connect . 3. Check the Same as Programming in Initialization before Debug Session section. 4. Edit the script parameters via the arrow button. If HOST debug protection...
Renesas RH850: Challenge & Response Authentication 03-Apr-2025
This topic describes how to enable PE and ICUM debugging using Python scripts when the Challenge & Response Authentication is enabled. Intelligent Cryptographic Unit Master (ICUM) is a RH850 HSM core that can run secure cryptographic operations. The ICUM is disabled at the device shipment....
NXP S32K3xx: Variable data flash size 29-Nov-2024
Data flash size of S32K3xx can change depending on Hardware Security Engine (HSE) firmware usage. Flash can have 3 different configurations: HSE firmware usage feature flag is disabled (no HSE firmware) HSE_B firmware usage feature flag is enabled (Full memory HSE firmware - HSE_FULLMEM) A...
NXP S32K14x: Mass erase is not working 26-Nov-2024
Most common reason is using authentication keys when partitioning the FlexRAM to EEPROM. Authenticating and removing this authentication by using CSEc keys is not supported by winIDEA. The partitioning can only be reversed manually. When no authentication keys are used , the EEPROM section...
Infineon AURIX TC3xx: Programming DFLASH1 when configured as HSM exclusive memory 26-Nov-2024
By default, Data Flash (DFLASH), which is divided into two banks DFLASH0 and DFLASH1, is programmed through the regular debug download (fast flash programming based on flash programming monitor) via Hardware | Infineon device | Configure. DFLASH can be split and used separately by the user...
Arm Cortex-M: Locked/secured device 18-Nov-2024
Possible solution 1. Select Debug |Prepare to Attach . 2. If using Hot Attach, follow the Hot Attach procedure to safely attach to the Target. 3. Select Hardware |Scripts |Unsecure (can also be Chip Erase or similar). This operation needs JTAG/SWD debug port to be accessible. Devices, wher...
Arm Cortex: The application does not stop after reset 12-Nov-2024
Possible solution Verify the RESET method selection in the Hardware |CPU Options |Reset. Explanation On Cortex devices internal reset logic can be implemented in various ways. The debug tool must be aware of the reset logic implementation to connect to the target microcontroller and gain c...
Arm Cortex / Texas Instruments AWR Family: Download to Local RAM fails 06-Nov-2024
When debugging a Texas Instruments AWR family device, it is possible that the RAM download after a reset/power cycle fails. Possible solution A soft reset is needed. Use the SoftResetCR4 script . More resources inwinIDEA Help Arm Cortex architecture-specific notes
NXP/ST Power Architecture: Cannot access SFRs on a Bolero device 22-Oct-2024
When trying to access SFRs on a MPC56/SPC56 Bolero device with 512 KB internal FLASH memory problems occur. Possible solution Write 0x80808000 to the CGM_SC_DC0 register (address 0xC3FE037C) before accessing any SFR and check if clock(s) for peripheral modules are switched on. This switche...
Infineon AURIX TC3xx: How to inject ECC error to PFLASH 19-Oct-2024
The scripts TC3xx_PFLASH_Inject_ECC_error.py and TC3xx_DFLASH_Inject_ECC_error.py , which are distributed with winIDEA, program a memory page to either PFLASH (address 0xA0000000) or DFLASH (address 0xAF000000).Then they turn auto ECC code generation OFF and use the same codefor reprogramm...
Flash programming fails 19-Oct-2024
Possible causes and solutions Use the latest verified build Open the Downloads web page. Wrong CPU selected Double-check the target CPU designation and verify that a matching CPU is selected in Debug |Configure Session |SoCs . CPU is reset by either external watchdog circuitry or internal ...
NXP/ST Power Architecture: Write to the OTP memory 17-Oct-2024
The best method to write to the One-Time-Programmable (OTP, also shadow, TEST, UTEST) Memoryregions is by running a script, which uses winIDEA SDK to connect to winIDEA. I t is recommended to verify the script accuracy before writing to the OTP Memory, since the OTP Memory can only be prog...
NXP/ST Power Architecture: When running the code it doesn’t reach main function 17-Oct-2024
When running the code after the download, it never reaches the main function. FLASH programming doesn’t report any verify error. Possible solution Simple manual Mass erase via Hardware |FLASH |Mass Erase before debug download may solve the problem already. Most probably the application rem...
Infineon AURIX / TC3xx: Rejecting FLASH operation. Start address not valid 17-Oct-2024
winIDEA checks if the start address from the Symbol file (ELF file) points to the same address specified in the STAD (Start address) field of any valid UCB (UCB_BMHDx_ORIG or UCB_BMHDx_COPY, BMHDx for x=0, 1, 2, 3). If it doesn’t, FLASH programming is rejected and a warning appears: Error ...
Renesas RH850/U2x: Hardware Property Area programming 16-Oct-2024
Hardware Property Area on U2x devices consists of seven areas, but the focus here is on the following four: Configuration Setting Area (CSA) Security Setting Area (SSA) Block protection area 0 (BPA0) Block protection area 1 (BPA1 is not available on smaller devices) Each of these areas is ...
Arm Cortex-M: Flash programming fails 16-Oct-2024
Check that the Flash memory is not secured or perform a special Unsecure operation (this erases Flash content). This can happen either by intentionally or accidentally writing to the memory locations managing the Flash security levels. Possible solutions Perform Reset action If a device us...
Arm Cortex TMS570: How to write to ECC? 15-Oct-2024
The TMS570 devices feature a Flash memory with optional ECC (Error correcting code) memory generation. ECC is generated in the ECC dedicated sectors, which are separated from the main Flash memory and can be programmed automatically or manually. Solution To be able to program your own ECC ...
Renesas RH850/F1KH/F1KM: The application is reconfiguring PLL 27-Sep-2024
If the application is reconfiguring the Phase-Locked Loop (PLL) after the device powers on, it might cause issues when attempting to access Option bytes. The issue happens since the FP5 method for Option byte access fails after PLL reconfiguration. Mass erasing all code/data from the flash...
Renesas RH850: Speed up the Flash programming 19-Sep-2024
To increase the Flash programming speed, you can use initialization files from pre-configured winIDEA Workspace Examples. Solution 1. Download winIDEA Example Workspaces . 2. Select a suitable Workspace. 3. The initialization file is by default added in Hardware | CPU Options | Initializat...
Renesas RH850 / P1x-C: UMI Error, R_FAD_ERR_CLOCK The CPU clock frequency is incorrect 17-Sep-2024
The CPU clock is determined by the PLL0 parameters in OPBT1. The factory default value is 0xBFFFC938, which cannot be used for Flash programming using UMI. Possible solution The Option byte OPBT1 PLL and Clock divider settings must be changed following RH850/P1x-C User's Manual device spec...
Renesas RH850 U2x/E2x: Download Verify ERROR 17-Sep-2024
Download from the primary winIDEA instance (core PE0 or CPU0) to the secondary winIDEA instance (core PE1 or CPU1) RAM fails. The reason for this is that winIDEA does not initialize the Local RAM of secondary cores. For the primary core, it is done partially by winIDEA to be able to perfor...
Infineon AURIX: How to disable Flash protection? 11-Sep-2024
Using dedicated initialization scripts, winIDEA can temporarily unprotect (and resume) Program Flash (PFLASH) Data Flash (DFLASH) Boot Mode Header Location (BMHD) before performing flash read/write operations into these areas. Flash protection password can be also entered as a script param...
Active Watchdog issues 14-Aug-2024
When an active External Watchdog / System Basis Chip (SBC) or Internal CPU Watchdog is not serviced properly, i t can cause problems such as: Unintended reset during Flash programming or Mass Erase operation Error 258:Failed to initialize debug session BlueBox loses control over the CPU af...
Mass erase doesn't work 14-Aug-2024
When trying to perform a Mass Erase of the chip, you get an error, e.g. UMI error. Formass erase to work, the CPU should be stopped. In case you have a multi-core device, the non-primary cores should be stopped as well. Possible solutions Enable theAllow mass erase option Enable this optio...
Renesas RH850 G3: Change Security ID code or Code/Data Flash passwords 14-Aug-2024
Changing the Security ID code or Code/Data Flash passwords is not supported in winIDEA. These security settings are critical for protecting your embedded system's firmware and data integrity, and altering them requires a more controlled and specialized process. Possible solution If you nee...
Renesas RH850/U2x: Double Map mode 14-Aug-2024
winIDEA supports both Single and Double Map Mode programming of Code Flash on Renesas RH850/U2x devices. Single and Double Map Mode are two memory map modes of Code Flash that can be selected by OPBT12. If Double Map Mode is used, Valid Area can be switched with OPBT13. Solution winIDEA au...
Renesas RH850: Flash programming fails 14-Aug-2024
Possible causes and solutions CPU reset caused by either External Watchdog circuitry or internal CPU watchdog Disable all reset sources during debugging to resolve the issue. More information is available in Active Watchdog issues . F1H, F1Kx: UMI Error R_FCL_ERR_FLMD0 FLMD0-Pin not at hig...
Arm Cortex AMD Zynq UltraScale+: DDR RAM Initialization 09-Aug-2024
To download and run an application in DDR RAM on AMD Zynq UltraScale+ using winIDEA, refer to Initialize AMD Zynq UltraScale+ DDR RAM how-to guide. More resources Add a custom initialization script
Arm Cortex Cypress Traveo II: Initialize Debug session via EVE script parameter 09-Aug-2024
winIDEA enables an alternate debug session initialization if issues with downloading occur. This only affects download operations. Possible solution 1. Add the custom initialization script to Hardware | CPU Options | Reset | Initialization before programming | Connect . 2. Select Yes in th...
Arm Cortex STM32H7: Configure flash 05-Aug-2024
Microcontrollers of the STMicroelectronics STM32H7 family have a special Flash Configuration Field where different settings for Flash programming can be adjusted. Possible solution 1. Open Hardware | device | Configure | FLAGS Configuration . 2. Configure according to your use case: Parall...
NXP S32Kxx: Programming Flash memory not possible 02-Aug-2024
When programming Flash memory of the S32K344 SoC using winIDEA version 9.21.109 or older, an error may occur, preventing you from programming the FLASH memory. Possible errors: Error programming UMI error Error loading monitor Possible solution Download the latest winIDEA build .
Arm Cortex ST Stellar: OTP memory programming fails 01-Aug-2024
winIDEA supports ST Stellar and Centauri MCUs like SR6G7 and SR6P7. Their n on-volatile memory (NVM, also Flash) parts, of which some are one-time-programmable (OTP), are represented in winIDEA through programmable memory devices such as CODE, DATA, and the two OTP BCS and UTEST. NVM also ...
Arm Cortex-M Cypress Traveo II 2M VIRGIN devices: Fail to establish debug session 01-Aug-2024
Debug session with Cypress Traveo II VIRGIN (life cycle) devices will be established partially - the core will not be stopped at the start of your application. Debugging VIRGIN devices is not supported from winIDEA 9.21.29. To inspect if you have a VIRGIN device refer to topic Reset and Fl...
Arm Cortex-M Cypress Traveo II: Reset and Flash programming fails 01-Aug-2024
If any issues with Cypress Traveo II occur, e.g.: Debug connection fails to establish Reset fails Flash programming fails Attaching to a core fails etc. follow the below procedure to troubleshoot. Possible solution 1. Enableloggingvia Help | Support | Log . 2. Check activity (27) EVE . 3. ...
Arm Cortex Cypress Traveo II: Reading from a Work Flash results in random data 01-Aug-2024
Work Flash is a flash memory used to store data (code storage for user application execution and local data storage/update for SoC-based systems). Work Flash is a part of the eCT Flash. Reading from a Work Flash that is still in an erased state will result in random data in the Memory Wind...
Arm Cortex-M: Application does not run correctly after download into Flash 01-Aug-2024
Two different applications (A and B) are added into a winIDEA workspace. Application A is debugged and then Application B is downloaded and debugged. Once the Application B is downloaded the core is not stopped on the correct reset vector. Running the core from this state results in Hard F...
Arm Cortex NXP Kinetis K2x/EA: Flash configuration 31-Jul-2024
Kinetis K2x The NXP Kinetis K2x series microcontrollers contain a 16-byte flash configuration field within the program flash memory. This field is essential as it stores default protection settings (loaded on reset) and security information, enabling the MCU to restrict access to the flash...
Arm Cortex Texas Instruments TMS570: ECC functionality 30-Jul-2024
Flash on TMS570 devices features an ECC functionality. The ECC area can be programmed automatically with values corresponding to downloaded data or you can provide your own ECC download data. The option for automatic ECC generation is located in Hardware | TI TMS570 | Configure | FLAGS Con...
Arm Cortex Microsemi SmartFusion2: Handling flash write threshold errors 18-Jul-2024
SmartFusion2 devices have threshold detection for the number of writes performed on flash memory. When this threshold is reached flash programming API returns an error status. Possible solution 1. Open Hardware | device | Configure | FLAGS Configuration . 2. Select IgnoreWriteThresholdErro...
Infineon AURIX: How to enable or disable debug password protection? 04-Jun-2024
The UCB Flash must be writable to configure the debug password protection. Using this procedure you may lock the device! Possible solution 1. Configure winIDEA to use a password via Hardware | CPU Options | SoC. 2. S et a password. Refer to the winIDEA Help Password protection chapter for ...
NXP/ST Power Architecture: Rejecting FLASH operation. No valid entry address in RCHW 30-May-2024
Before performing a FLASH download, winIDEA verifies if the Entry point address specified in the Symbol file (ELF file) matches the Application start address specified in the first valid RCHW record of the download image. If this doesn't match, FLASH programming is rejected and a warning i...
Renesas RH850: Option Bytes Programming 24-May-2024
Possible solutions To change the option bytes you can use: RH850 Option Bytes plugin - winIDEA 9.21.94 or newer Refer to the winIDEA Help topic Option Bytes plugin . Service calls -winIDEA 9.21.8 or newer Service calls are used for FP5 communication from. Refer to winIDEA Help chapter Opti...
Infineon AURIX TC3xx: Do not use Fill Memory to clear UCB section 28-Mar-2024
Filling the whole block of memory with any value using function Fill Memory in the Memory Window in order to clear UCB section of AURIX devices will LOCK the chip. More resources in winIDEA Help Storage programming Memory window