Categories

NXP/ST Power Architecture
NXP/ST Power Architecture / SPC58: Accessing Performance Monitor Registers (PMR) 29-Nov-2024
Before accessing thePerformance Monitor Registers (PMR) both Internal Debug Mode (IDM) and Performance Monitor Interrupt (PMI) bits must be set in the External Debug Resource Allocation Control (EDBRAC0) register. See the EDBRAC0 register structure below: The default value for EDBRAC0 regi...
NXP/ST Power Architecture: Download/reset does not work 22-Oct-2024
Certain PowerPC chips have escalation counters. These counters will keep track of consecutive resets and, if there are too many in a short time, the chip goes into a permanent reset. As a result, winIDEA cannot establish a debug session since the chip is in reset. Solution The solution is ...
NXP/ST Power Architecture: Target memory access 22-Oct-2024
Various cores within the PowerPC e200 family include an MMU (Memory Management Unit). For these particular cores to be able to access their program space memory, the MMU needs to be configured and TLB (Translation Look aside Buffer) entries have to be created at start-up. Variables located...
NXP/ST Power Architecture: Cannot access SFRs on a Bolero device 22-Oct-2024
When trying to access SFRs on a MPC56/SPC56 Bolero device with 512 KB internal FLASH memory problems occur. Possible solution Write 0x80808000 to the CGM_SC_DC0 register (address 0xC3FE037C) before accessing any SFR and check if clock(s) for peripheral modules are switched on. This switche...
Missing program code 22-Oct-2024
If a Missing program code message is displayed in the trace, it means that the program was executed at addresses where no code image is available in the download file. The debugger needs a complete code image for the correct trace reconstruction. The code not reported in the download file ...
NXP/ST Power Architecture: Password protected device 19-Oct-2024
When a device is password protected, BlueBox must send the password to the device to unlock the debug interface. Before that only access to JTAG ID was available. The p assword is entered in Hardware | CPU Options | SoC . Possible solutions 64-bit password The password is accepted by MPC/S...
NXP/ST Power Architecture: How to write to the OTP memory? 17-Oct-2024
The best method to write to the One-Time-Programmable (OTP, also shadow, TEST, UTEST) Memoryregions is by running a script, which uses winIDEA SDK to connect to winIDEA. I t is recommended to verify the script accuracy before writing to the OTP Memory, since the OTP Memory can only be prog...
NXP/ST Power Architecture: MMU TLB Entry for this address not found 17-Oct-2024
Possible problems and solutions Go To option is used before the MMU is configured Do not use the Go To option in Debug | Configure Session | SoC | Startup dialog, the application will configure MMU accordingly. PC counter after the CPU reset is preset, MMU is not configured for the address...
NXP MPC563xM: Slew rate of Nexus pins 17-Oct-2024
An errata is related to the Nexus port on MPC563xM devices. The slew rate on Nexus pins remains slow when Nexus is enabled. Possible solution Use the initialization sequence below to change the slew rate of Nexus pins. Check the errata document for your target device to see if this issue i...
NXP/ST Power Architecture: SFR access and peripheral module power status 17-Oct-2024
When accessing SFRs on MPC5xxx / SPC 5x devices problems occur. Possible solution 1. Check if clock(s) for peripheral modules are switched on. 2. Use the initialization sequence in the Hardware | CPU Options | Reset dialogto enable access to the peripheral modules. 3. Add this write also t...
NXP/ST Power Architecture: When running the code it doesn’t reach main function 17-Oct-2024
When running the code after the download, it never reaches the main function. FLASH programming doesn’t report any verify error. Possible solution Simple manual Mass erase via Hardware |FLASH |Mass Erase before debug download may solve the problem already. Most probably the application rem...
NXP/ST Power Architecture: Trace trigger doesn't work – Analyzer remains in WAITING state 17-Sep-2024
Nexus Event Out Pin (EVTO) signal is used in winIDEA as a trace trigger, but it is not enabled. Possible solution To generate the trigger event (EVTO), enable it in the Trigger Configuration window: 1. Open View | Analyzer . 2. Click the Analyzer Configuration button. 3. Check the Manual H...
NXP/ST Power Architecture: Trigger point (frame 0) position is not displayed 17-Sep-2024
With Nexus trace, which is a message based trace, actual trigger point (frame 0) is most likely not be displayed next to the instruction which generated the trigger event. The Nexus trace port broadcasts only addresses of non-sequential branch jumps. All the sequential code in between is r...
NXP/ST Power Architecture: How to configure general CPU settings? 31-Jul-2024
These configuration steps arerequired to connect BlueBox to the Target andperform CPU Reset, which establishes initial Debug connection. Solution 1. Create a New Workspace via File | Workspace | New Workspace . 2. Set JTAG Scan speed in Hardware | CPU Options | JTAG . 3. (optional) Enter p...
The debugger cannot connect to the Target 31-Jul-2024
If you are experiencing issues with establishing debug session, follow the below tips: Possible solutions Power-cycle your device and try to perform a reset This way you will pinpoint the issue either with: Establishing debug session (if reset fails as well) or Flash programming (if reset ...
Failed to initialize debug session / Emulation start failed 30-Jul-2024
The error means that the debugger failed to connect to the target CPU. This can be for different reasons. When troubleshooting the initial debug connection to the target CPU, it is recommended to use the CPU Reset instead of Download. Possible causes and solutions BlueBox is not properly c...
NXP/ST Power Architecture: Rejecting FLASH operation. No valid entry address in RCHW 30-May-2024
Before performing a FLASH download, winIDEA verifies if the Entry point address specified in the Symbol file (ELF file) matches the Application start address specified in the first valid RCHW record of the download image. If this doesn't match, FLASH programming is rejected and a warning i...
NXP/ST Power Architecture: Access to an unallocated address stops the CPU 27-May-2024
If memory access to an unallocated address is executed (e.g a pointer in Watch window), the microcontroller stops working. Possible solution This state can be exited only by issuing reset. Use debug windows with caution to prevent accidentally accessing such locations.
NXP/ST Power Architecture / MPC560x, SPC560P, SPC560B: Watches & Disassembly showing illegal instructions 29-Apr-2024
Whenever a pointer is added in the Watch Window and an element is expanded in it, then debugging proceeds, all values get corrupted and in the Disassembly Window displays message Illegal Instructions . The content of the pointer is not modified, it is only read. Possible solution Avoid rea...
NXP/ST Power Architecture: Trace does not work when in SAFE mode 18-Apr-2024
MPC5675 K can stay in SAFE mode which disables the MCKO signal and the trace does not work. Possible solution Use the below init sequence which switches CPU from SAFE into DRUN mode: A RGM_FES W 0x4080 A ME_MCTL L 0x30005AF0 A ME_MCTL L 0x3000A50F
MPC551x: Internal Watchdog resets the CPU while debugging 04-Apr-2023
Possible solutions Disable internal watchdog The Internal Watchdog must be disabled because the Watchdog is not stopped when the application is stopped (microcontroller is in the debug mode). In such case, the Watchdog could reset the microcontroller while the application is stopped and th...