Due to a limitation of the RH850G3 debug interface, a customer application runs for a while before a debugger can start a FP5 protocol access. During this time, the application could disable FP5 access to the target device, a condition that cannot be restored even after reset, except after a power cycle. Follow the procedure below for a workaround.
1. Turn OFF the device.
2. Make sure that you have enabled Check Vref on startup in Hardware > SoC options > Hardware.
3. Open an OPBT plugin or run the script to disable the ICUM, for example.
4. When the progress bar shows the message Vref out of range. Waiting for 30s to turn ON the device, turn ON the device. FP5 access should now be working.
The Progress window displays an error:
Device FP5 query: FP5 Serial communication error! Please check External Oscillator and FP5 frequency (baudrate) settings
The error means that the device is not responding to FP5 commands. An incorrect oscillator frequency setting is the most common cause of the error.
1. Go to Hardware > SoC Options > Debugging.
2. Verify that the Ext. Oscillator clk setting matches the on-board quartz crystal connected to the RH850 device.
This setting is required for FP5 serial communication only (e.g. to access RH850G3 SoC Option bytes). LPD debug session does not use it.
3. Power-cycle the RH850 target board and retry. Usually, power cycling is not needed, except for some rare persistent cases.
For problem analysis, it is recommended to use winIDEA logging capability:
FP5 is short for the Renesas RH850 PG-FP5 serial protocol. It is intended for device flash factory programming. With winIDEA, it is normally used when executing Python scripts to read and write RH850G3 SoC Option bytes, or OPBTs, that define user configuration of the device.
Debug
pins are also used for the FP5 communication. To be able to communicate
the SoC factory firmware needs to know the frequency of the external
quartz oscillator; therefore, winIDEA communicates
the value to the device firmware. This is the only way for the firmware
to correctly configure a device PLL and thus be able to communicate
efficiently at high baud rates and program the device flash with correct
timing parameters.
Note, winIDEA does not use FP5 protocol with RH850G4 SoCs.