In some cases, an update of the SFRs in winIDEA can take tens of seconds. Therefore, it is recommended to create a custom SFR group with the SFRs of interest. With a custom SFR window, you can: Manage a large number of SFRs via a custom SFR window Monitor specific SFRs through the Watch wi...
Possible problems and solutions Go To option is used before the MMU is configured Do not use the Go To option in Debug | Configure Session | SoC | Startup dialog, the application will configure MMU accordingly. PC counter after the CPU reset is preset, MMU is not configured for the address...
XMC devices implement a special functionality for stopping the CPU at the reset vector after reset when the debugger is connected. Possible solution 1. Go to Hardware | CPU Options | Reset | Reset pin. 2. Select the Regular Reset method. More resources in winIDEA Help Reset - Dialog refere...
Since AURIX is a highly security-oriented device, it is by default not possible to apply the debug password at any time, but rather only in a very short period of time after a Power on, Application or System reset. This fact is very important when dealing with Application and System resets...
Possible solutions Command line Use the following compiler command line option (for Generate Target-Walkable Stack) : -gtws To get maximum debug information with GHS Compiler follow this link . Calls tack Generation Probe different callstack options, e.g. if Automatic does not work, try wi...
Infineon DAS Wiggler plugin enables the Infineon DAP miniWiggler directly within winIDEA to allow direct programming and debug control of AURIX devices. Supported IDEs and licensing 32-bit winIDEA version 9.21.48 or higher 64-bit winIDEA version 9.21.48or higher with DAS V7.0 The tool is f...
Renesas RL78 devices have On-Chip debug security ID setting area. The values programmed to this device memory area are compared to the values of the bytes set in the winIDEA. If these two do not match, you get different effects when trying to debug this device like: RL78 ERROR Unlock ID co...
Code Read Protection (CRP) is a mechanism that allows you to enable different levels of security in the system so that access to the on-chip flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in Flash location at 0x000002FC. If value 0...
When trying to establish a debug session, the message Reset is INACTIVE appears in the Progress window and/or log file. Explanation The reset line state is reported for informational purposes . It is the state sensed on the reset signal of the debug connector. Message is usually informativ...
winIDEA stores various temporary files in %TEMP%/iSYSTEM , or if specified, %ISYSTEM_TEMP% directory. Most of the created files are meant to speed up your debugging experience and they remain there even after winIDEA is closed. winIDEA will clean up such files regularly, but depending on w...
CC265xx devices support configuring the DIO pin on which the Serial Wire Output (SWO) trace is output. Possible solution 1. SWO output must be connected to the TDO pin of the Arm adapter. 2. Select cJTAG Debug Protocol in Hardware | CPU Options | SoC . Since the JTAG protocol uses TDO for ...
Before accessing thePerformance Monitor Registers (PMR) both Internal Debug Mode (IDM) and Performance Monitor Interrupt (PMI) bits must be set in the External Debug Resource Allocation Control (EDBRAC0) register. See the EDBRAC0 register structure below: The default value for EDBRAC0 regi...
To be able to write to the SFR register, you need to use the modify() call. Possible solutions Drag and drop an item to the Watch Window This way, you will get the correct syntax and find out the name of the SFR. Use this syntax in P ython Backslash '' \ '' in P ython is also used as an in...
For Texas Instruments AWR18xx and AWR68xx devices, the ROM must be eclipsed with the RAM content after the bootloader. This process requires manual enabling of ROM eclipsing, followed by a soft reset. Possible solution 1. Select Hardware | Scripts | SoftResetCR4 . 2. Retry Download once th...
On LPC15xx devices, you can configure I/O pin to use for a SWO trace with a custom initialization script. Environment will remap the selected pin to output SWO trace, disabling any function previously assigned by the application. Possible solution 1.Add the custom script LPC15xx_TraceInit....
The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code, or, in the case of the LPC13xx, it can obtain the boot image as an attached MSC device through USB. A LOW level during reset at pin PIO...
Per LPC435x specification, Cortex-M0 is not accessible through the SWD debug interface. It’s accessible only through the JTAG debug interface. It’s recommended to use the JTAG debug interface when debugging LPC435x, which allows debugging both Cortex-M4 and Cortex-M0 cores . If only the SW...
Programming applications to a microcontroller can take a lot of time, especially if the application is large, the storage device is external memory and the data rate is slow. Possible solutions Minimize download time - general settings Check the frequency of the debug interface and set up ...
How to download new code/data when the application temporarily allows debug port access? For security reasons, your application can block access to the debug port,restricting readout or tampering of the firmware.In such a case, there is often some special code written in the application th...
When observing only a subset of registers on a SoC with many SFRs the followinginconveniences can be encountered: Focusing only on the items of interest and skipping the rest, e.g., by scrolling through the registers. Refreshing the content of irrelevant items can affect responsiveness. Po...
When AURIX devices are in debug mode, Watchdog is enabled by default , but the Watchdog Timer is unconditionally suspended (stopped), which means that the Watchdog never resets the chip. To use the Watchdog during debugging, you have to disable the Watchdog Timer suspended logic (or enable...
This guide helps with the transition from using the INI files to using winIDEA GUI settings to configure synchronization and peripheral suspension. If you are also migrating from an old winIDEA version, please refer to the general transition guide as well. In the older winIDEA versions ( 9...
Solution These command line options provide maximum debug information when using GHS Compiler: dual_debug full_debug_info Omoredebug You should not use ignore_debug_references compiler command line option. For more information refer to Missing callstack information when using GHS Compiler ...
Possible causes An External Watchdog resets the chip periodically. Faulty hardware: Target, Debug Adapter, or Active Probe. CPU is always in reset or the debugger cannot reset the CPU. Bad contact if the CPU is in a socket. DAP Wide mode is selected in Hardware |CPU Options |SoC , however,...
Access to cache data Access to cache data is enabled by default on Cortex-M devices in winIDEA, requiring no additional configuration. Understanding cache behavior and real-time observability While the default behavior is sufficient in most cases, certain debugging scenarios require additi...
Error 304 means the BlueBox fails to connect and establish a debug session with theCortex-M-basedtarget CPU. Possible solutions Use the Reset debug command When troubleshooting the initial debug connection to the target CPU, it's recommended to use the CPU Reset debug command instead of th...
With the TriCore plugin core window Counters, y ou can measure the time between two functions, e.g. between main, which starts counters, and startOS, which stops counters. Solution Refer to the how-to guide in winIDEA Help.
The voltage levels for the debug interface are configured within winIDEA via the CPU Options dialog. Solution Make sure Vref is selected for Debug I/O levels, otherwise, the debug session fails or may behave unpredictably. 1. Open Hardware | CPU Options | Hardware . 2. Select the Vref opti...
The LPC4357 is a dual-core with ARM Cortex-M4 and Cortex-M0 cores, which are accessed via the following Debug Protocols: Cortex-M4 on JTAG and SWD Cortex-M0 only on JTAG By default winIDEA tries to connect to all available cores. When selecting the SWD Debug Protocol, winIDEA should connec...
Possible causes The variable is changing, but Real-time Memory access still shows the initial value. In this case, the variable may be cached, which makes Real-time Memory access impossible. The variable value is not updated in the Watch and Memory windows Note that using any of these solu...
After issuing a Resetin winIDEA, the primary core (Cortex-M0+) is stopped at the reset vector, while the secondary core(s) are IDLE (Debug status IDLE will be shown). The secondary core(s) are then started by the application running on the primary core. Configuring Hardware |CPU Options |C...
The JTAG chain is configurable within Zynq SoC. Cascaded JTAG works with an empty device. You must provide a soft core to connect external pins to Arm DAP if Independent JTAG mode is desired. Refer to Mode Pin Settings and JTAG and DAP Subsystem chapters in the Zynq reference manual for mo...
You would like to synchronize: The basic debugging operations across multiple winIDEA instances, independent of the BlueBox platform and processor family The execution of a custom Python script using winIDEA SDK Possible solution With emuSync you can keep track of many different winIDEA ap...
The Callstack Window doesn't show current call stack content or the displayed info is incorrect. Possible solutions Compiler optimization The compiler can optimize the code to the extent that the required information being used by the debugger to extract theCall Stackcontextis not availabl...
Variables missing from the structure or two structures in the ELF with the same name but slightly different types are usually caused by compiler excessive code optimization. Possible solution winIDEA offers an option to control the resolution of variable locations from Symbol table. 1. Ope...
The following applies only in winIDEA 9.21.99 and older. When the regular Special Function Registers (SFR) window is expanded, winIDEA tries to read all of the expanded SFR registers. As soon as there is an access error, it stops reading the SFR registers and prints out the error message S...
In most RH850 devices the Local RAM is accessible from different addresses via a core bus and a DMA bus. By default, a faster, DMA bus access is set. Normally the core's Local RAM is accessible at the "self area" address by its core only. Note that if the download code is linked at the cor...
DAP over CAN Physical Layer Converter (DXCPL) enables debugging via the regular CAN pins of the ECU connector without opening its housing. This connection is electrically robust due to the nature of the CAN bus. The DXCPL Converter translates Infineon AURIX™ SPD (Single Pin DAP) encoded DA...
When using the winIDEA Memory window to view memory that should be inaccessible, you may notice a discrepancy in the memory display between the Virtual and IPmemory areas. Specifically, the Virtualmemory area displays "00" values instead of the expected "??," while the IP memory area corre...
Some possible reasons for this error to occur: Watchdog issues Clock source for CPU is set with higher frequency than allowed or predictable CPU suspended / in reset / running in sleep mode No debug line symbol available to put the breakpoint to stop the CPU winIDEA cannot attach to the co...
These c onfiguration steps are required to connect BlueBox to the Target and perform the CPU Reset command, which establishes the initial Debug connection. Possible Solution 1. Create a New Workspace via File | Workspace | New Workspace . 2. (optional) Make sure LPD is set on the target de...
System reset or download (Error 258) fails on XMC1000 and NXP LPC family devices, when the debugger uses the reset vector catch mechanism to stop the CPU after the CPU reset release. Possible solution Always leave the CORERESET exception unchecked. 1. Open Hardware | CPU Options | CORE0 . ...
When launching winIDEA, IDE Special Function Registers (SFRs) are expanded to a dedicated SFR location on your computer. If winIDEA detects that the SFR database is corrupt, missing, or does not match the winIDEA version, it restores it. Note that the SFR database could get corrupt if eith...
Certain PowerPC chips have escalation counters. These counters will keep track of consecutive resets and, if there are too many in a short time, the chip goes into a permanent reset. As a result, winIDEA cannot establish a debug session since the chip is in reset. Solution The solution is ...
How to avoid unneeded issues with peripheral devices when debugging the application? Possible solutions Suspend peripherals while stopped Use the Hardware | CPU Options | Reset | At Initialization | Suspend peripherals while stopped option and select the peripheral functions you want to be...
Various cores within the PowerPC e200 family include an MMU (Memory Management Unit). For these particular cores to be able to access their program space memory, the MMU needs to be configured and TLB (Translation Look aside Buffer) entries have to be created at start-up. Variables located...
While debugging, some functions (or source lines) cannot be stepped over. The dialog Step Operation in Progress appears. If the CPU is run, the same function executes normally. One of the possible root causes for such behavior is that the function that is being stepped over uses interrupts...
When a device is password protected, BlueBox must send the password to the device to unlock the debug interface. Before that only access to JTAG ID was available. The p assword is entered in Hardware | CPU Options | SoC . Possible solutions 64-bit password The password is accepted by MPC/S...
Possible solutions Delayed power ON target Because of the hardware limitation of the BlueBox, the application runs for a bit before starting FP5 access. During that time, an application could disable FP5 access to the target device, which is not restored even after reset (but only after th...
JTAG Chain scan functionality enables you to define IR/DR Prefix/Postfix values which could be entered in Hardware |CPU Options |JTAG . That is important when several devices are connected in a chain and you want to debug for example the second one. Possible solution From winIDEA build 9.2...
Possible causes Emulation start failed Instable connection Download not working UMI errors Write to Memory Window fails or memory read fails Solution Upgrade ST-Link firmware using ST firmware upgrade tool.
The Debug Entry feature in Hardware | CPU Options | Cores allows you to configure per-core startup actions. To access the Debug Entry settings for the boot core, go to Debug | Configure Session | SoCs | Startup. Use cases Want to debug a core immediatelyafter it is released from reset? 1. ...
Callstack display is one of the fundamental tools in the debugging process. Solution: 1. Open the Callstack Window via View | Debug | Callstack . 2. Set a breakpoint in the function. 3. Observe the entire callstack of the beginning of the execution up to the breakpoint. 4. Observe how to s...
An errata is related to the Nexus port on MPC563xM devices. The slew rate on Nexus pins remains slow when Nexus is enabled. Possible solution Use the initialization sequence below to change the slew rate of Nexus pins. Check the errata document for your target device to see if this issue i...
When accessing SFRs on MPC5xxx / SPC 5x devices problems occur. Possible solution 1. Check if clock(s) for peripheral modules are switched on. 2. Use the initialization sequence in the Hardware | CPU Options | Reset dialogto enable access to the peripheral modules. 3. Add this write also t...
Solution Each winIDEA version has a unique build number with a committed number, e.g. 9.21.222 (162707). 1. Open Help | About winIDEA . 2. The build number is located at the bottom of the window:
If the CPU starts to behave unpredictably (e.g., the debug session status changes from the expected state RUN or STOP to SoC Attaching or Initialized ), ensure you are not making any unintended memory reads. Possible solution Close all debug windows and see if this resolves the problem. Th...
While establishing a debug session with the secondary core by performing Download an error appears: Cannot connect to server RC1 . Possible solutions Open ports 5235 and 5304 Open these ports in the Windows Defender Firewall or any other hardware or software firewalls you are using. When d...
Sometimes the Target CPU can end up in an unrecoverable state after the debug session is established and operational . Neither performing the Download or Reset command regains winIDEA control over the Target CPU. Possible solution Try to restart the whole setup via a Power Off/On cycle. Co...
winIDEA shows question marks "??" in the Memory Window whenever a memory read at a specific memory location fails. Possible reasons No physical memory is present at the specific memory. The debug interface memory read command fails for some reason. The memory is not accessible after the mi...
Use the Directories page to help winIDEA locate (or share) the source code referenced in Symbol Files . This is necessary to allow source-level debugging. Possible solutions You can locate files: From View | Symbols From an open Editor document If the original path to the source files is k...
Maximum debug interface frequency ensures that under all circumstances the debug interface communication works reliably, which is especially important during FLASH programming, where in the worst case an error in transmission could cause the CPU/SoC device failure. Higher debug interface f...
With the SFR dump method, you can determine what CPU registers were changed between two points (e.g. between reset and some function, function entry and exit, CPU reset, and CPU initialization, etc.) and find issues via low-level debugging by revealing and comparing the content of two CPU ...
Find a bug in your code using basic debugging principles: Breakpoint bisecting Stepping into and over the code Using microcontroller documentation For a m ore detailed visualization of the whole configuration procedure follow the Breakpoint bisecting Tutorial .
Watchdog periodically resets your system which can cause problems such as u nintended reset during flash programming or mass erase operation, failed debug session, etc.; however it can detect failures, e.g., if your system has hung or it is no longer executing the correct sequence of code....
When the CPU executes a (watchdog) reset, it triggers a CORERESET exception. By default, the debugger is set to catch such an exception and halts the CPU, which is indicated by the STOP-VCATCH Debug status. Possible solution 1. Open Hardware | CPU Options | Cores . 2. Make sure CORERESET i...
Solution To disable ENDINIT protection and be able to change the registers, add this line to any initialization file: A CBS_OCNTRL L 0x000000C0 // Disable ENDINIT More resources in winIDEA Help Initialization sequence Internal Flash programming
The procedure described below generates a searchable text file containing the same information (address, data, debug symbol, opcode, operands...) as in the Disassembly window. With this, you can: Find opcodes Find a ccesses to specific addresses (e.g. write to SFR register) Disassemble a s...
When an active External Watchdog / System Basis Chip (SBC) or Internal CPU Watchdog is not serviced properly, i t can cause problems such as: Unintended reset during Flash programming or Mass Erase operation Error 258:Failed to initialize debug session BlueBox loses control over the CPU af...
For WLCSP packages, the boot loader changes the default pin configuration to: PIO0_2 register - SWCLK PIO0_3 register - SWDIO TCK_PIO0_5 register - PIO0_5 SWDIO_PIO0_10 register -PIO0_10 Possible solution Connect PIO0_2 and PIO0_3 to the debug connector for debugging. More resources in win...
Traveo II devices require a debug interface operating at a frequency higher than 1500 kHz. This permits the debugger to execute the necessary debug initialization procedures fast enough and within the device start-up time window constraint after the CPU reset line is released by the BlueBo...
The peripherals on Traveo II devices, such as timers, are not frozen by default when the device is halted in debugging. CYT4DN CYT4BF CYT4BB CYT3DL CYT3BB CYT2BL CYT2B9 CYT2B7 CYT2B6 Possible solution Custominitialization scripts are distributed with winIDEA to freeze the Traveo's peripher...
Password and Challenge/Response authentication are secure debug modes that prevent unauthorized access to the SoC by requiring correct credentials at the start of a debug session. Once authenticated, the SoC remains unsecured until a power-on-reset or similar reset occurs. For Password aut...
While using winIDEA you encounter an error related to debug password configuration, e.g. Debug access failed . Possible solutions Verify endianness It's possible that the endianness of the provided password is incorrect. For example, if you programmed the password into UTEST as 0x00, 0x01,...
Additional configuration is required when using Attach/Detach procedure in conjunction with the workaround proposed to the M7 application core hung state erratum (ERR051149). Refer to the NXP errata documentation for a more detailed description and the proposed workaround. Solution Perform...
Possible solutions LPC devices The most common cause is that the image programmed in the Flash prevents any further debug access or connections and fails to establish a debug session. The image usually contains code that: Sets the SoC clocks up incorrectly Enables a watchdog timer This put...
On Cortex-M devices from the LPC family a Boot Rom is present with: Code that is executed on reset A memory mapping register (MEMMAP, SYSMEMREMAP) After the debug connection is established: The target core is released from reset and stopped at the beginning of the boot code. The initial st...
These topics describe how to start debugging the Arm Cortex-M7 and A53 / Arm Cortex-M33 or Cortex-R52 cores if no valid boot image is found on: Cold Start with NXP S32G/S32R Arm Cortex-M7 or A53 core Cold Start with NXP S32E2/Z2 Arm Cortex-M7 or A53 core
The flash bootloader code is executed every time the part is powered on or reset. The loader can execute the ISP command handler or user application code. A LOW level after reset at pin P2.10 is considered an external hardware request to start the ISP command handler. Assuming that power s...
With Target Download functionality you can write to memory from a file without resetting your target system. Solution 1. Open Debug |Configure Session |SoCs | Target Files . 3. Add files via the Add button you want to write to the target memory. 4. Go to the Startup page and s elect Target...
The implemented update affects the following features: Option Bytes Programming Refer to Option Bytes Programming . Challenge & Response winIDEA 9.21.8 and newer Use EVE scripts to unlock the debug Interface. Refer to Challenge & Response Authentication . winIDEA 9.21.7 and older Unlock th...
TriCore architecturally does not have a mechanism that would allow the CPU to be stopped when a trap (in some other architectures known as an exception) occurs.Various mechanisms can trigger traps on the core, such as null pointer dereference or data alignment errors. Possible solutions Sc...
If memory access to an unallocated address is executed (e.g a pointer in Watch window), the microcontroller stops working. Possible solution This state can be exited only by issuing reset. Use debug windows with caution to prevent accidentally accessing such locations.
winIDEA can displaydescriptive bit field Enums in the Watch window. Solution 1. Open Debug |Debug Options| Symbols . 2.Select an option from Enum display drop-down list: Enum - Displays the value as an Enum. Integer - Displays the value as a number. Enum (Int) - Displays value in both repr...
You can unlock the TexasInstruments TMS570 device with the AJSM unlock keyin winIDEA for temporary debug access. More information in winIDEA Help TMS570: AJSM Unlocking .
Possible errors are: CPU variant not found Invalid SoC Error reading INI file (Errors when trying to perform memory writes contained in an initialization file) SoC not specified Empty Programmable memory devices list in Hardware |Options Empty Boot Core selection in Hardware |CPU Options |...
Using software breakpoints impacts the checksum result. The debugger inserts a dedicated “software breakpoint” instruction on addresses where software breakpoints are set. These “software breakpoint” instructions are not visible, e.g. in the Disassembly or Memory Window at software breakpo...
You can debug i.MX 8QuadMax M4 Processor cores using boot image where all application cores are booted and using boot image where only M4_0 core is booted. More information in winIDEA Help How-to guide Debugging i.MX 8QuadMax M4 Processor .
The program flash memory on S32K1xx devices contains a specific region that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFC module. This topic describes how to allow programming in winIDEA in this region that ...
Debugging (step in, step over...) a target application is working until the StartOS function is called. This function initializes the System timer (STM). On TC3xx devices usually that is the STM0 timer. The timer is used by the scheduler to switch between the tasks. If you want to debug su...
Possible solution 1. Close all debug windows in winIDEA. 2. R un the application from the reset state on. This ensures that the debugger doesn’t access any Target CPU resources while the application is running. This also best mimics Target running standalone without the debugger connected....
Standby Controller (SCR) is an 8-bit microcontroller that can continue to run during standby mode. It is based on the XC800 Core which is compatible with the industry standard 8051 processor and is available on selected TC3xxx devices. SCR core is selectable in winIDEA as any other core. S...